SCHEMATIC DIAGRAM FOR 8~BIT PARALLEL PARITY GENERATOR

The Philippine Electronics and Technology Forum > Digital Electronics > General Digital Design (Moderator: marcelino) > SCHEMATIC DIAGRAM FOR 8~BIT PARALLEL PARITY GENERATOR

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Zerokraust

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SCHEMATIC DIAGRAM FOR 8~BIT PARALLEL PARITY GENERATOR

« on: February 25, 2010, 09:53:48 PM »

Sirs Help naman po dito, schematic po ng 8~bit parity Gen thanks!


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SCHEMATIC DIAGRAM FOR 8~BIT PARALLEL PARITY GENERATOR

« on: February 25, 2010, 09:53:48 PM »


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rdpzycho

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Re: SCHEMATIC DIAGRAM FOR 8~BIT PARALLEL PARITY GENERATOR

« Reply #1 on: March 01, 2010, 01:14:30 AM »

XOR lang naman ang Parity. multi-bit XOR, mag-1 ang output niya kapag odd ang number ng 1's. kung odd parity ok na. kung even parity, invert lang 'yung output ng XOR. Wink


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carlsfootprints

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Re: SCHEMATIC DIAGRAM FOR 8~BIT PARALLEL PARITY GENERATOR

« Reply #2 on: March 06, 2010, 01:36:51 AM »

ganito ba un sir? Cheesy


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