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EL SEGUNDO, Calif. — International Rectifier, IR® (NYSE: IRF), a world leader in power management technology, today introduced a series of industrial-qualified 30V TO-220 HEXFET® power MOSFETs with extremely low gate charge (Qg) for applications including Uninterruptable Power Supply (UPS) inverters, low voltage power tools, ORing applications and netcom and server power supplies.

The robust MOSFETs feature IR’s latest generation Trench technology and offer very low on-state resistance (RDS(on)) to reduce thermal dissipation. In addition, the new devices’ ultra low gate charge helps extend battery life of UPS inverters or power tools.

“The new devices offer the best cost and performance tradeoff. Moreover, by offering four levels of RDS(on) and Qg at a 30V level, the devices provide design engineers with the flexibility to select the optimum device to match their specifications and requirements for the application,” said Hemal Shah, marketing manager for IR’s Power Management Devices Business Unit.

The new MOSFETs feature fully characterized avalanche voltage and current and are direct replacements and upgrades to existing 30V TO-220 devices as IR continues to develop benchmark MOSFETs.

The devices are qualified to industrial grade and moisture sensitivity level 1 (MSL1). The 30V MOSFETs are available in a TO-220 package, are offered lead free and are RoHS compliant.

Price and Availability

The new devices are available immediately. Pricing begins at US $0.22 each and US $0.25 each for the IRLB8721PbF and IRLB8748PbF respectively, while the IRLB8743PbF and IRLB3813PbF cost US $0.32 and US $0.63 respectively in 10,000-unit quantities. Pricing is subject to change.

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Connor-Winfield’s 5 x 3.2 mm M Series TCXOs/VCTCXOs are designed for use in Stratum 3 applications, GPS receivers, Instrumentation, Femtocell, FTTH and FTTC or any other application requiring tight frequency stability in a small package. Through the use of Analog Temperature Compensation, this device is capable of holding sub 0.28ppm holdover over multiple temperature ranges. Stratum 3 freerun is guaranteed for 20 years. Outputs are available as LVCMOS or clipped sine wave.

Product Features:
• 3.3V Operation | 5.0V Operation
• LVCMOS or Clipped Sinewave Output Logic
• Sub-Miniature 5×3.2 mm SMT Package
• Frequency Stabilities Available:
> ±0.28 ppm with Stratum 3 Holdover
> ±0.50 ppm or 1.00 ppm
• Temperature Ranges Available:
> 0 to 70°C
> -40 to 85°C
• Low power (2mA typ @16.384 MHz Clipped Sine)
• Low Jitter <1pS RMS ( 12kHz to Fo/2)
• Low phase noise
• Low aging
• Tape and Reel Packaging
• RoHs Compliant
• Recommended for new designs

For more information contact:
The Connor-Winfield Corporation
Tel: 630.851.4722
www.conwin.com
sales@conwin.com

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SUSS MicroTec, a leading supplier of process and test solutions for the semiconductor and related industries, and the Belgian nanoelectronics research center IMEC have entered a joint development program. Together, they will develop permanent bonding, temporary bonding and debonding processes for 3D system integration, including through-silicon-via (TSV) manufacturing.

IMEC will use SUSS MicroTec’s XBC300 production wafer bonder platform to develop 200 and 300mm permanent metallic interconnect bonding, as well as temporary bonding and debonding solutions for its 3D-stacked Interconnect and 3D Wafer Level Packaging technology. This universal platform can support a wide range of materials and processes, and allows debonding dies at room temperature, which is an important condition for the integration of memory ICs and CMOS image sensors. The bond cluster also includes a spin coater, a low force bonder and a plasma chamber.

For its 3D IC technology, IMEC uses a process flow where TSVs are realized in a single-damascene process that is performed immediately after front-end and contact processing but prior to processing of the back-end metallization layers. This process enables small via diameters of 1–5µm. After completion of the back-end wiring, silicon is removed from the bottom of the substrate to open the buried TSVs. Dies or wafers subsequently are stacked and interconnected in a wafer bonding step.

“We are very pleased to co-develop with SUSS MicroTec the processes for permanent and temporary wafer bonding for our 3D technologies,” said Eric Beyne, Program Director of IMEC’s Advanced Packaging and Interconnect Research Centre. “In particular, the debonding and handling of very thin wafers ranging from 25 to 50µm is an especially challenging and critical process. We are convinced that the versatility of the SUSS wafer bonding and debonding tool platform will contribute to bringing 3D integration technology to maturity.”

“Working with IMEC, a premier research facility, on 300mm 3D development for temporary and permanent bonding applications is an exciting opportunity for SUSS MicroTec,“ said Wilfried Bair, General Manager, SUSS MicroTec’s Bonder Division. “This cooperation is clearly in the path of our strategic engagement with leading industry partners at the fore-front of development. The co-development combined with our focus on understanding our customers’ needs will help us to continuously provide state-of-the-art technology and solutions to our customers today and tomorrow.”